1. Field of the Invention
This invention relates to a method of making a semiconductor package, and more specifically to a method of making a semiconductor package by dicing a wafer from the back side surface thereof.
2. Description of the Related Art
As electronic devices have become more smaller and thinner, the velocity and the complexity of IC chip become more and more higher. Accordingly, a need has arisen for higher packaging efficiency. Demand for miniaturization is the primary catalyst driving the usage of advanced packages such as chip scale packages (CSP) and flip chips. Both of them greatly reduce the amount of board real estate required when compared to the alternative ball grid array (BGA) and thin small outline package (TSOP). Typically, a CSP is 20 percent larger than the chip itself. The most obvious advantage of CSP is the size of the package; that is, the package is slightly larger than the chip. Another advantage of CSP is that the package facilitates test and burn-in before assembly as an alternative to known good die (KGD) testing. In addition, CSP can combine many of the benefits of surface mount technology (SMT), such as standardization, encapsulation, surface mount, and reworkability, with the benefits of flip chip technology, such as low inductance, high I/O count, and direct thernmal path.
However, as compared with conventional BGA or TSOP, CSP has the disadvantage of higher manufacturing cost. However, this problem could be eliminated if the chip-sized packages could be mass produced more easily. Therefore, the semiconductor packaging industry has tried to develop mass production techniques at the wafer-level for manufacturing the chip-sized packages, as illustrated in U.S. Pat. No. 5,323,051, U.S. Pat. No. 5,925,936 and U.S. Pat. No. 6,004,867.
For the methods of making the chip scale package disclosed in U.S. Pat. No. 5,323,051and U.S. Pat. No. 5,925,936, the methods substantially comprise the steps of: a) encapsulating an active surface of a wafer; b) grinding the encapsulated wafer to expose the bumps on the active surface of the wafer and to obtain the predetermined thickness; and c) dicing the encapsulated wafer according to the exposed bump as positioning reference marks.
In the above mentioned patents, the exposed bumps are utilized as the positioning reference marks for dicing the encapsulate wafer. But the exposed bumps of the individual chip or dice is too tiny to provide an obvious positioning reference mark which is easily detected by the positioning device of the dicing machine or apparatus. Hence, the positioning device of the dicing machine or apparatus is often positioned with errors.
U.S. Pat. No. 6,004,867, entitled xe2x80x9cChip-size Package Assembled Using Mass Production Techniques At The Wafer-Levelxe2x80x9d issued on Dec. 21, 1999 to Kim et al., discloses a chip-size package technique at the wafer level, wherein a substrate is attached to an active surface of a packaged wafer, the substrate includes grooves or index patterns corresponding to the scribe lines, and the grooves or index patterns in the substrate will be exposed by grinding such that the exposed grooves or index patterns are utilized as positioning reference marks for dicing the wafer. However, according to the process of the invention, the wafer requires additional attachment of the substrate for dicing, which fails to fully meet the requirements of chip scale package.
Moreover, due to the demand for miniaturization and high operating velocity, it is more desirable to apply the multi-chip package to a variety of electronic devices. The multi-chip package assembles two or more chips into a single package, so as to minimize the limitation of the operative speed of the electronic system. Besides, the multi-chip package would shorten the length of wires between bumps to reduce the signal delay and I/O time.
Typical multi-chip package is side-by-side multi-chip package in which two or more chips are set side-by-side on a main surface of a common substrate. The electrical connections between the chips and the common substrate are usually achieved by wire bonding. However, the side-by-side multi-chip package has the disadvantage of low packaging efficiency because the area of the common substrate would increase as the number of chips increases.
Hence, Taiwan Patent Application. 089109786, entitled xe2x80x9cStacked Multi-chip Packagexe2x80x9d, filed on May 19, 2000 by this applicant, discloses a stepped chip structure wherein the stepped chip can be attached on another chip to form a multi-chip package. According to the invention, two chips are stacked on a multi-chip module substrate such that the bottom of the upper chip would not contact with the loop profile of the bonding wire of the lower chip so as to overcome the disadvantage of prior stacked chip package. However, the above mentioned patent application did not provide a suitable method or process to dice the wafer to obtain the stepped chip structure.
Moreover, in the prior technique, the cavity down configuration is well known and is widely applied in ball grid array (BGA) package. But the prior technique did not provide a suitable stacking method and structure for the cavity down configuration to package a plurality of chips on the same area of the substrate.
Therefore, a need exists for a semiconductor package that provides a method for dicing wafer so as to overcome the above mentioned drawback.
It is a primary object of the present invention to provide a method of dicing a wafer from the back side surface thereof so as to accurately dice the wafer into individual dices or chips.
It is a secondary object of the present invention to provide a method of dicing a wafer from the back side surface thereof for mass producing chip-size package at the wafer-level so as to reduce the cost of manufacturing chip-size package.
It is another object of the present invention to provide a method of dicing a wafer from the back side surface thereof for forming a stepped chip structure.
It is still another object of the present invention to provide a method of dicing a wafer from the back side surface thereof for forming a cavity down configuration chip structure.
In order to achieve the objects mentioned hereinabove, there is provided a method of dicing a wafer from the back side surface thereof. According to the present invention, the method comprises the steps of:
a) providing a wafer having an active and a back side surface, the active surface of the wafer having a plurality of scribe lines defining individual chips;
b) forming a through structure corresponding to the scribe lines on the active surface of the wafer; and
c) dicing the wafer from the back side surface of the wafer according to the through structure as positioning reference marks.
According to one aspect of the present invention, the through structure is composed of two grooves perpendicular to each other.
According to another aspect of the present invention, the through structure is a plurality of indented grooves on the perimeter of the wafer.
According to a further aspect of the present invention, the through structure is a lacuna.
According to a further aspect of the present invention, the method of dicing a wafer from the back side surface thereof further comprises the steps of encapsulating the wafer with molding compound and grinding the molding compound and the back of the wafer before the step of dicing the wafer to form a chip-size package.
According to another further aspect of the present invention, the method of dicing a wafer from the back side surface thereof further comprises the step of forming slots on the back side surface of the wafer with a wider width before the dicing process so as to form a stepped chip structure having an outer tier and a central tier.
According to another further aspect of the present invention, the method of dicing a wafer from the back side surface thereof further comprises the step of forming cavities on the back side surface of the wafer before the dicing process so as to form a chip having a cavity down configuration.
According to the present invention, the through structure on the back side surface of the wafer are able to provide obvious positioning reference marks to accurately and rapidly dice the wafer into individual dices or chips in the dicing process. Moreover, the method of dicing a wafer from the back side surface thereof according to the present invention also provides the stepped chip and the cavity down chip for forming a multi-chip package.